The devices for generating a clock signal by frequency multiplication offer the advantage of having a low power consumption while at the same time being free of jitter limitations in the long term.
Furthermore, the multiplication factor can be flexible and such devices can quickly come to a lock.
The solutions currently used are notably solutions based on phase-locked loops that are totally analog, totally digital or else analog and digital.
However, analog and analog/digital phase-locked loops operate within a limited range of power supply voltage and require design precautions in order to take into account the stability constraints in closed-loop mode. Furthermore, the design of purely analog phase-locked loops is complicated, whereas entirely digital phase-locked loops have an output frequency limited by the frequency range of the oscillator.
Another solution that has been envisaged resides in direct digital synthesis, but such a solution is limited in frequency.